1. Field of the Invention
Embodiments of the present invention relate generally to a memory device and more particularly to a method of programming the memory device.
2. Description of the Related Art
Types of memory devices may be divided into volatile and nonvolatile memory devices depending on whether data stored therein is maintained when a power supply is cut off. A volatile memory device loses its data when the power supply is cut off, and includes DRAM and SRAM. A nonvolatile memory device maintains data even though the power supply is cut off, and includes a flash memory.
FIG. 1 is a diagram illustrating one block in a conventional nonvolatile memory device.
Referring to FIG. 1, the memory block includes a plurality of cell strings 110 to 160. Each of the cell strings 110 to 160 includes a plurality of memory cells, a drain selection transistor, and a source selection transistor. The plurality of memory cells are controlled by a plurality of word lines WL0 to WL63, respectively. The drain selection transistor uses a drain selection line DSL to electrically couple the cell strings 110 to 160 to bit lines BLe_0 to BLe_N and BLo_0 to BLo_N. The source selection transistor uses a source selection line SSL to electrically couple the cell strings 110 to 160 to a common source line CSL.
Memory cells controlled by one word line are divided into an even page corresponding to the even bit lines BLe_0 to BLe_N and an odd page corresponding to the odd bit liens BLo_0 to BLo_N. That is, memory cells controlled by the same word line and corresponding to the even bit lines BLe_0 to BLe_N form one even page, and memory cells controlled by the same word line and corresponding to the odd bit lines BLo_0 to BLo_N form one odd page. In FIG. 1, since a total of 64 word lines WL0 to WL63 exist, one memory block includes 64 even pages and 64 odd pages. Depending on the configuration of a memory block, even pages and odd pages may not be discriminated.
In general, the operation of a nonvolatile memory device includes a read operation of reading stored data, an erase operation of erasing stored data, and a program operation of storing data. The erase operation is performed in memory block units, and the read operation and the program operation are performed in page units.
FIG. 2 is a diagram illustrating a conventional single page program method.
Referring to FIG. 2, a program command and an address are applied to a memory at step S210, and program data corresponding to a single page is loaded into a page buffer at step S220. Then, a program pulse is applied to program memory cells within a page selected by the address at step S230, and whether threshold voltages of the program memory cells within the page reaches a target threshold voltage is verified at step S240. According to the verification result, if the threshold voltages of all the cells reached the target threshold voltage, the program operation is ended. Otherwise, a program pulse is reapplied at step S250. Once the threshold voltages of all the cells have reached the target threshold voltage, the program operation for one page is ended, and a program operation for the next page is performed.
In the single page program method, after a program operation for one page is completed, a program operation for the next page is performed. However, coupling and interference occur between memory cells. Accordingly, when a memory cell is programmed, the threshold voltages of memory cells around the memory cell may be changed. For example, during a program operation of a page corresponding to the word line WL3, the threshold voltages of memory cells within pages corresponding to the word lines WL2 and WL4 may also change. When such a phenomenon is accumulated, data stored in the memory cells may be changed. As a result, the reliability of the memory may be significantly reduced.
In order to overcome such a problem of the single page program method, Korean Patent Laid-open Publication No. 2008-0114386 and so on have proposed a multi-page program method which sequentially program a plurality of pages little by little. In this method, however, because the respective pages are programmed little by little, a time required for the program operation drastically increases. Therefore, it is not easy or efficient to apply the multi-page program method to an actual memory.